Purpose

Follows the pattern established in #53065 (XPU Triton fused MoE tuning): port
benchmarks/kernels/benchmark_w8a8_block_fp8.py to Intel XPU and ship tuned
Triton kernel configs for the W8A8 blockwise FP8 GEMM (block_shape=[128,128])
on Intel(R) Arc(TM) Pro B70 Graphics.

Changes

• benchmarks/kernels/benchmark_w8a8_block_fp8.py: XPU support (platform
  assert, device_type, guard torch.cuda.init(), and a curated
  get_xpu_tuning_space() — 96 configs vs. 1280, since per-config Triton
  JIT compile time on B70 is ~1-8s vs. sub-100ms on CUDA; only used when
  current_platform.is_xpu())
• 26 new tuned config JSONs under
  vllm/model_executor/layers/quantization/utils/configs/ for
  device_name=Intel(R)_Arc(TM)_Pro_B70_Graphics,dtype=fp8_w8a8,block_shape=[128,128]
  (comparable to MI300X's 28 and H20/H100/H200's 23-26 for this kernel),
  covering dense-linear shapes from DeepSeek-V3, DeepSeek-V2-Lite
  (TP=1), Llama-3.1-8B (TP=1, packed QKV/gate-up), and Qwen3-8B's two
  shapes not already covered by Llama's

Results

Intel Arc Pro B70, fp8. Baseline is the kernel's built-in default config
(BLOCK_SIZE_M=64, GROUP_SIZE_M=32, num_warps=4, num_stages=2, used when no
tuned JSON is found); tuned uses the generated JSON. Per-batch sweeps (10
sizes, matching the tuned grid) for two DeepSeek-V2-Lite (tp=1) shapes;
geometric-mean speedups are 2.73x (N=576,K=2048, kv_a_proj_with_mqa /
kv_b_proj) and 2.00x (N=22016,K=2048, gate_up_proj):

Numerical validation: every tuned config was checked against an FP32
reference GEMM using deterministic FP8 block-quantized inputs (relative L2
error < 2e-2). DeepSeek-V2-Lite passed 60/60 batch-size x shape
combinations; Llama-3.1-8B passed 60/60; Qwen3-8B's 2 newly-tuned shapes
passed 40/40 (its other 2 shapes reuse Llama-3.1-8B's already-validated
configs, see below).

End-to-end

Served yiliu4/DeepSeek-V2-Lite-Chat-Block-wise-FP8-Test-Only (block-FP8
checkpoint) on a single B70 card. Both rows use explicit
--linear-backend triton, comparing Triton's built-in per-shape heuristic
(baseline) with the tuned shape-specific JSONs. Workload: 512 input tokens,
128 output tokens, 32 prompts, inf request rate; 1 warm-up run discarded, 3
measured runs per arm (seeds 2-4):

For reference, the default (oneDNN, auto) path is substantially faster
than tuned Triton on all four models (roughly 2-5.7x), confirming the
"Note on scope" above: this PR's value is the tuning pipeline plus configs
for whenever Triton is the selected/needed path, not a claim that Triton
should replace oneDNN on B70.

Test plan

• Tune on XPU with
  benchmark_w8a8_block_fp8.py tune --tp-size <tp> --batch-size <bs>.
• Verify every generated winner against an fp32 reference
  (relative L2 error < 2e-2).
• Confirm serving with --linear-backend triton loads the exact JSON
  (fp8_utils.py logs Using configuration from ... for W8A8 Block FP8 kernel.).
• Compare the kernel's default config and tuned config with identical
  inputs at the tuned batch-size grid.
• Compare heuristic and tuned Triton E2E with identical workloads and fresh
  engines.
• Keep CUDA/ROCm behavior unchanged; XPU pruning is guarded by
  current_platform.is_xpu().