SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus

Virtual development board for HDL design

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Verilog VPI module to dump FST (Fast Signal Trace) databases

Interfacing VHDL and foreign languages with VUnit

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

Virtual Pi Library for mocking Raspberry Pi

a lightweight Verilog-vpi Wrapper for Stimuli Generation

RSA_Encryption/Decryption DATA using MATLAB & VPI Library

A generic verification interface to Verilog simulators using TCP sockets

An IcarusVerilog VPI bridge for the Swift Programming Language.

Using Nim to interface with Verilog and SystemVerilog test benches via VPI

vpi introduction thru examples

Multi-device optimization of asynchronous ORB-SLAM2 algorithm with CUDA exploitation.

edge perception stack that turns stereo vision and LiDAR into localized 3D observations

RustDV-based RTL verification environment for a 4-bit TinyALU using directed testing, deterministic randomized regression, functional coverage, corner-case testing, scoreboard checking, VPI simulation, and GTKWave waveform analysis.

An IEEE-1364 VPI interface for CXXRTL (the Yosys C++ simulation backend), so cocotb can drive CXXRTL models.

NVIDIA DeepStream GStreamer plugin for AprilTag detection on Jetson Orin NX/AGX using VPI 3 and the PVA (Programmable Vision Accelerator). Supports 4 simultaneous RTSP streams with zero CUDA core usage.