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soft-core
Here are 35 public repositories matching this topic...
A small, light weight, RISC CPU soft core
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Sep 16, 2026 - Verilog
💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
open-source microcontroller fpga processor vhdl gcc customizable msp430 soc soft-core system-on-chip msp430-gcc
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Nov 23, 2021 - VHDL
🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.
computer-science cpu fpga processor riscv verilog computer-architecture hdl soc verilog-hdl risc-v soft-core rv32i system-on-chip riscv32 dhrystone rv32 processor-design basic-rv32s risc-v-learn
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Feb 2, 2026 - Verilog
A fully automated, custom CPU and software stack for tiny embedded systems
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Oct 11, 2025 - Go
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
c tutorial cpu fpga vhdl assembler open-hardware fpga-game sd-card vga 16-bit soft-core system-on-chip vhdl-examples qnice learn-fpga fpga-tutorial vhdl-tutorial
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Sep 22, 2026 - Assembly
Open source ISS and logic RISC-V 32 bit project
linux c-plus-plus fpga processor iss embedded-systems verilog cpu-model risc-v soft-core 32-bit risc-processor co-simulation
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Sep 1, 2026 - Verilog
Basic UART TX/RX module for FPGA
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Oct 18, 2018 - Verilog
Superscalar OoO RISC-V CPU, marchid: 50 (0x32), RVA22S64/RVI20U32.
emulator fpga riscv systemverilog out-of-order microarchitecture speculative soft-core riscv32 riscv64 soft-cpu rva23 rva22
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Oct 26, 2026 - SystemVerilog
A RISC-V RV32IM CPU and SoC built from scratch in SystemVerilog — single-cycle → 5-stage pipeline, caches, AXI4 + DDR, HDMI — running DOOM on a Zybo Z7-20. Spike-verified, Verilator-simulated.
cpu fpga zynq pipeline cache processor doom riscv rtl verilog xilinx hdmi systemverilog computer-architecture soc risc-v soft-core verilator rv32im axi4
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Jun 20, 2026 - SystemVerilog
LatticeMico32 instruction set simulator project
linux c-plus-plus embedded fpga processor gdb iss python3 tcp-socket debug tkinter risc cpu-model 32-bits soft-core serial-communication latticemico32 com0com
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Sep 4, 2025 - C++
Trying to implement a soft core SoC
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Apr 6, 2019 - Verilog
Extended RISC-V soft core targeting the Basys3 FPGA: RV32IM + Zba + Zicsr/Zifencei/Zicntr on a 5-stage in-order pipeline with a branch predictor. Runs FreeRTOS with an interactive shell in Verilator simulation; formally verified multiply/divide unit. Built on TU Graz's HaDes-V.
cpu fpga riscv freertos vivado systemverilog computer-architecture rtos hdl formal-verification risc-v basys3 wishbone soft-core verilator processor-design artix-7
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Oct 27, 2026 - Assembly
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