Digital Audio Noise Filtering with MATLAB and Verilog This project implements a complete end-to-end system for detecting and filtering noise from real-world audio using a combination of MATLAB signal processing and Verilog hardware design. Starting from spectral analysis and filter synthesis in MATLAB, it proceeds to fixed-point audio formatting,

An industry-standard FPGA Traffic Light Controller designed in SystemVerilog (FSM-based) featuring an interactive Python Streamlit co-simulation control dashboard and comprehensive EPWave verification.

A parameterizable and synthesizable single-clock-domain Digital Clock core with integrated Alarm, Snooze, and 12/24-hour display modes implemented in Verilog HDL. Features double-register button debouncing and a time-multiplexed 7-segment display driver.