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1. Project-Zipline Project-Zipline Public

   Forked from opencomputeproject/Project-Zipline

   Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

   Verilog 2 1

2. riscv-v-spec riscv-v-spec Public

   Forked from riscvarchive/riscv-v-spec

   Working draft of the proposed RISC-V V vector extension

   Assembly

3. Adafruit_ILI9341 Adafruit_ILI9341 Public

   Forked from sifive/Adafruit_ILI9341

   Library for Adafruit ILI9341 displays

   C++

4. learn-fpga learn-fpga Public

   Forked from BrunoLevy/learn-fpga

   Learning FPGA, yosys, nextpnr, and RISC-V

   C++

5. cvw cvw Public

   Forked from openhwgroup/cvw

   CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

   Assembly

6. verilator verilator Public

   Forked from verilator/verilator

   Verilator open-source SystemVerilog simulator and lint system

   SystemVerilog