rookiephysicist · GitHub
Skip to content
View rookiephysicist's full-sized avatar
2 followers · 7 following

Block or report rookiephysicist

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. UART-communication-Link-on-a-FPGA-using-Verilog-HDL UART-communication-Link-on-a-FPGA-using-Verilog-HDL Public

    Forked from ChandulaNethmal/UART-communication-Link-on-a-FPGA-using-Verilog-HDL

    This post is regarding a HDL implementation of a UART(Universal Asynchronous Receiver Transmitter) for one of our university fourth semester projects.For the project we were supposed to implement a…

    Verilog

  2. Processor-Design-and-Implementation-on-a-FPGA Processor-Design-and-Implementation-on-a-FPGA Public

    Forked from ChandulaNethmal/Processor-Design-and-Implementation-on-a-FPGA

    Overview The objective of this project is to design object specified microprocessor and a Central Processing Unit in order to downscale an image. As steps of above task, we have to simulate it usin…

    Verilog

  3. LiFi LiFi Public

    Forked from SemihAkkoc/LiFi

    The implementation of LiFi protocol on the BASYS3 Xilinx Artix-7 board using VHDL.

    VHDL

  4. 5-Stage-Pipelined-MIPS32-RISC-Processor-Design-on-Verilog 5-Stage-Pipelined-MIPS32-RISC-Processor-Design-on-Verilog Public

    Forked from arpit306/5-Stage-Pipelined-MIPS32-RISC-Processor-Design-on-Verilog

    This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined configuration.

    Verilog

  5. Elevator-Control-System-using-Verilog Elevator-Control-System-using-Verilog Public

    Forked from Ankit-kumar65/Elevator-Control-System-using-Verilog

    Elevator Controller for 60 floors building using Verilog code

    Verilog

  6. Implementation-of-CDMA-Transmitter-and-Receiver-using-Intel-DE2i-150-FPGA-board Implementation-of-CDMA-Transmitter-and-Receiver-using-Intel-DE2i-150-FPGA-board Public

    Forked from darshangm92/Implementation-of-CDMA-Transmitter-and-Receiver-using-Intel-DE2i-150-FPGA-board

    Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the digital modulation technique and Altera FFT MegaCore Functio…

    Verilog