ridash2005 (Rickarya Das) · GitHub
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Achievements

Achievement: Pair ExtraordinaireAchievement: YOLOAchievement: QuickdrawAchievement: Pull Shark

Achievements

Achievement: Pair ExtraordinaireAchievement: YOLOAchievement: QuickdrawAchievement: Pull Shark

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ridash2005/README.md

⚡ Technical Arsenal

🔩 Hardware Engineering

Category Skills & Tech Stack
HDL Verilog SystemVerilog VHDL Chisel
Architecture RISC-V ARM SoC Design AXI/AHB
Simulation Vivado ModelSim Quartus Icarus Verilog
EDA Synopsys DC Cadence Virtuoso OpenROAD Magic VLSI
Protocols PCIe AXI I2C SPI UART JTAG
Verification UVM Formal Verification Cocotb

💻 Software Engineering

Category Skills & Tech Stack
Languages Python C++ C JavaScript TypeScript Rust Go
Frontend React Next.js Tailwind CSS TypeScript
Backend Spring Boot FastAPI Node.js Django Flask REST API Apache Maven
Databases PostgreSQL MongoDB Redis SQLite
Systems & OS Linux Bash Assembly Makefile
Testing PyTest Jest Postman

🤖 AI / ML Engineering

Category Skills & Tools
AI / Machine Learning PyTorch TensorFlow JAX Scikit-learn Hugging Face
Deep Learning & GenAI LangChain LlamaIndex YOLO CLIP
Data & Computer Vision NumPy Pandas OpenCV
Software & Web React Next.js Tailwind CSS FastAPI Django Flask

☁️ DevOps, Cloud & Infrastructure

Category Tools & Infrastructure
Cloud Platforms AWS GCP Azure
Containers & Orchestration Docker Kubernetes
CI/CD GitHub Actions GitLab CI
Infrastructure as Code Terraform Ansible
Observability Prometheus Grafana

🌟 Featured Projects

⚙️ Bit-Serial Neural Engine

Designed and implemented an low-power neural computation accelerator utilizing bit-serial arithmetic. Won 1st place in Hackathon, NIT Jamshedpur - 2025. (In collaboration with VLSI FOR ALL)

🔗 View Project

🧠 Systolic Array CNN Accelerator

Developed a high-throughput 2D systolic array matrix multiplication engine optimized for CNN workloads. Synthesized and verified on Xilinx FPGAs using Vivado, achieving high resource utilization and optimized clock frequencies.

🔗 View Project

🔌 FPGA Buck Converter Controller

Developed a high-performance discrete-time voltage-mode PID controller for a synchronous buck converter. Implemented on a Xilinx Spartan-7 FPGA with 23-bit fixed-point precision and parallel hardware execution.

🔗 View Project

📡 Offline Distributed UPI System

Built a decentralized, mesh-routed offline payment system for zero-connectivity environments. Features store-and-forward gossip protocols and hybrid RSA/AES-GCM encryption for secure offline transactions.

🔗 View Project

🗄️ Text-to-SQL with Oracle AI

Demonstrated natural language to SQL translation using Oracle AI Database 26ai's Select AI feature. Implemented interactive Jupyter notebooks to automate SQL query generation from plain English prompts.

🔗 View Project

⚡ CUDA Kernels — GPU Engineering

Developed high-performance custom CUDA kernels for fundamental deep learning operations (SGEMM, 2D convolution, and FlashAttention-style primitives). Optimized memory access patterns via shared memory tiling, coalescing, and register usage to bridge the software-hardware gap.

🔗 View Project

📊 Developer Metrics

🏆 GitHub Trophies

🔌 Let's build the future — from gates to gradients.


"The best AI systems are designed by engineers who understand the silicon they run on."

   

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Popular repositories Loading

  1. Systolic-Array-based-Hardware-Accelerator-for-CNNs Systolic-Array-based-Hardware-Accelerator-for-CNNs Public

    A parameterizable Systolic Array Hardware Accelerator for CNNs implemented in SystemVerilog, optimized for high-throughput Matrix-Matrix Multiplications (GEMM) with an RTL-to-GDSII flow.

    Verilog 5 1

  2. HAL-Zero-Protocols HAL-Zero-Protocols Public

    Embedded Communication Suite: Bare-metal STM32F4xx drivers (Zero-HAL), Industrial Protocol Stacks (Modbus RTU, CAN 2.0B, USB CDC), and FPGA RTL implementations with E2E verification across C, Syste…

    C 4 1

  3. AlphaStream_Final AlphaStream_Final Public

    AlphaStream India is a production-grade, real-time investment intelligence terminal designed to empower Indian retail investors. Featuring a Bloomberg-style terminal UI, it integrates Gemini 2.0 Fl…

    Python 4

  4. Bit-Serial_Neural_Computation_Engine Bit-Serial_Neural_Computation_Engine Public

    High-efficiency, resource-optimized Neural Network Computation Engine in SystemVerilog. Leverages bit-serial arithmetic to minimize hardware footprint (LUTs/Registers) without compromising precisio…

    SystemVerilog 3

  5. Hierarchical-Cache-Design Hierarchical-Cache-Design Public

    A modular and fully synthesizable 3-level (L1/L2/L3) cache memory subsystem implemented in SystemVerilog, featuring split L1 caches, a centralized L2, and a Last-Level L3 cache with coherence support.

    SystemVerilog 3

  6. GNN-based-Fraud-Detection GNN-based-Fraud-Detection Public

    GraphGE: Uncertainty-aware fraud detection on Bitcoin transactions using GraphSAGE. Implements Bayesian uncertainty quantification via Monte Carlo Dropout, class-imbalance mitigation, and selective…

    Jupyter Notebook 3