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[arch] ADR-001 also needs DDR3L clarification on top of bandwidth amendment (Stays #28)

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

Status: Open.

#33 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[arch] Amend ADR-001 — DDR3 bandwidth claim 12.8 GB/s is theoretical, real is 1.5-2.4 GB/s on ECP5+open toolchain

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

Status: Open.

#32 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[cross-stream] interconnect block port surface must match InnerJib7EA intercard_link stub

cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination needed

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

Status: Open.

#29 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[arch] Decide whether contr_rd_data should also be wire (asymmetry with core1_rd_data)

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

Status: Open.

#28 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[hw] Re-verify single-deep contr_rd_pending latch when gpu_controller.sv migrates

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

Status: Open.

#21 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[hw] Delete src/global_mem_controller.sv when gpu_die.sv migrates to direct AXI4 adapter (PR-2b)

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

Status: Open.

#20 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[cross-stream] inter-card link bandwidth + latency model for scheduler

cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination needed

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

stream-3Software Stack (Agent 3) — driver, runtime, GGML, SpankerSoftware Stack (Agent 3) — driver, runtime, GGML, Spanker

Status: Open.

#18 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[cross-stream] expose queryable axi4_mem_model state for ggml-spanker integration tests

cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination needed

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

stream-3Software Stack (Agent 3) — driver, runtime, GGML, SpankerSoftware Stack (Agent 3) — driver, runtime, GGML, Spanker

Status: Open.

#17 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[cross-stream] LitePCIe has no ECP5 PHY — rev-A host-link path is unsupported upstream

cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination needed

human-attentionStrategic / financial / governance — needs humanStrategic / financial / governance — needs human

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

stream-2FPGA Hardware (Agent 2) — KiCad, Stays primaryFPGA Hardware (Agent 2) — KiCad, Stays primary

stream-4Open FPGA Upstream (Agent 4) — yosys, prjtrellis, LiteDRAM patchesOpen FPGA Upstream (Agent 4) — yosys, prjtrellis, LiteDRAM patches

Status: Open.

#13 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[meta] Operating model 4+1 active — Sprint 7EA-W1 kickoff

metaSprint coordination, planningSprint coordination, planning

Status: Open.

#11 In popsolutions/MAST;

· marcos-mendez opened on May 6, 2026

[arch] ADR-014 — Inter-card link architecture choice (multi-card parallelism)

cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination needed

stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primary

Status: Open.

#9 In popsolutions/MAST;

· marcos-mendez opened on May 5, 2026