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Simple mono FM Radio.
SystemVerilog 50 31
FPGA USB 1.1 Low-Speed Implementation
Verilog 36 8
RISC-V Ibex core with Wishbone B4 interface
SystemVerilog 22 4
Forth CPU J1 in SystemVerilog
Forth 19 5
Swift implementation of Peter Norvig's constraint based solver.
Swift 13 1
Forth CPU J1 in SystemVerilog and Wishbone interface
SystemVerilog 9 2
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