My final project for ELEC2602, a superscalar 16bit microprocessor
The typical execution cycle is represented by the state machine below. To achieve parallel execution this state machine is being used on two different instructions at once, the val of PC and PC+1, if an error would occur due to data depency or PC jumping the result of the instruction at PC+1 is simply not saved to a register, everything else still occurs.
Written using Quartus 17 although it should work with any VHDL software.
Set top level entity to "processor.vhd" and fire away