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LiteWing drone modified for simplification by cutting down unnecessary traces and pins
HTML
An automated benchmarking pipeline using ReFrame, Spack, and Slurm with real-time Grafana visualization
Python
Verilog code for labs done in digital system design lab, including, but not limited to, single path risc processor
VHDL
FPGA UART driver. push bits from FPGA to pc terminal using UART PMOD
Updated as I learn more about UVM
location tracking in a 1 mile range w/ gps module and hc-12 module on arduino
C++
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