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A simple Verilog SPI master / slave implementation featuring all 4 modes.
Verilog 89 15
Controlling WS2812b RGB LEDS with STM32 HAL and timers
C 4 2
Yew hybrid rendering
Rust 2
Forked from ZiyangYE/General-Slow-DDR3-Interface
A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
Verilog 2
Forked from miniwinwm/BluePillDemo
A collection of small example projects tailored for the Blue Pill board created in STM32CubeIDE. No further updates.
C 1
Forked from bl0x/learn-fpga-amaranth
Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
Python 1
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