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NVDLA small config implementation on Zynq ZCU104 (evaluation)
Verilog 24 12
Out-of-the-box CHaiDNN implementation on Zynq ZCU104
C++ 9 5
RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.
Verilog 13 11
Generate UVM testbench framework template files with Python 3
SystemVerilog 26 7
Get Netease music lyrics + timestamps with Python 3
Python 3
An imitation of the Binding of Isaac with cocos2dx
C++
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