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Forked from YosysHQ/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Verilog
Forked from efabless/raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Forked from stnolting/neorv32
A small and customizable full-scale rv32imacuZicsr_Zifencei RISC-V CPU and SoC written in platform-independent VHDL.
VHDL
Forked from syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilog
Forked from ejrh/cpu
A very primitive but hopefully self-educational CPU in Verilog
Forked from BrunoLevy/learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
C++
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