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SystemVerilog implementation of the Bendix G-15. Captured manually from original schematics.
SystemVerilog 2 1
Forked from adafruit/Adafruit_CircuitPython_Logging
Logging module for CircuitPython
Python 1
Cycle-accurate IBM 650 simulator written in C++
C++
Forked from steveicarus/iverilog
Icarus Verilog
Forked from verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
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