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6-stage pipelined RV32IM processor in SystemVerilog, closing timing at 100 MHz on Artix-7 after evolving from a 5-stage design capped at 64 MHz. Pipelined hardware multiplier, iterative divider, M-…
Real-time cricket batting game on the TI MSPM0G3507 (ARM Cortex-M0+) with triple-ISR architecture, custom KiCad PCB, 5-bit DAC audio, and 3D-printed enclosure. Built for ECE 319H at UT Austin.
High-efficiency power conversion circuit that steps down a higher input voltage to a lower output voltage for a load. Unlike simple methods such as resistor dividers, which dissipate energy as heat…
12-state Moore FSM four-way traffic light controller in Verilog HDL with protected left turns, all-red safety interlocks, and 100MHz-to-1Hz clock divider. Deployed on Basys 3 (Artix-7).