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Forked from DECAfpga/BrianHG-DDR3-Controller
DDR3 Controller, 16 read, 16 write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included.
SystemVerilog 2
LiteX + Tang nano 9K run under Windows powershell/WSL
Python 2
RISC-V RV32I[C] CPU (Apache-2.0) - Merlin
Verilog 1 1
Forked from scarv/xcrypto
XCrypto: a cryptographic ISE for RISC-V
Verilog 1
Forked from helloworld1983/OpenROAD-example
Hello World
Forked from amaranth-farm/fpga-mandelbrot
The Terasic DECA board as a mandelbrot acceleerator
Python 1
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