Issues

• #304 breaks sky130 LVS on PDK revisions without special_nfet_01v8 (59 test regressions; live on stable)

  VLSIDA/OpenRAM#334 · Filter by author mguthaus opened on Oct 21, 2026

• 23_lib_sram_linear_regression_test: shares the default model's goldens, and the model emits negative leakage power

  VLSIDA/OpenRAM#333 · Filter by author mguthaus opened on Oct 21, 2026

• Liberty goldens are stale: 8 of 10 23_lib_* test combinations fail on clean dev

  VLSIDA/OpenRAM#328 · Filter by author mguthaus opened on Oct 16, 2026
  1

• magic DRC run from stdin reports 0 before the check runs

  VLSIDA/OpenRAM#327 · Filter by author TheAnimatrix opened on Oct 16, 2026
  1

• gen_stimulus.py probes the all-ones address and has a TypeError in the spare-rows branch

  VLSIDA/OpenRAM#326 · Filter by author TheAnimatrix opened on Oct 14, 2026
  2

• Please Help: LVS error on 1024x8bit ROM (new user)

  VLSIDA/OpenRAM#319 · Filter by author gsomlo opened on Oct 7, 2026
  2

• [Community Tool] openram-rom-libgen: ROM Timing & Power Characterization, Liberty (.lib) and Behavioral SystemVerilog Models

  VLSIDA/OpenRAM#318 · Filter by author EUB-RN opened on Oct 5, 2026

• Gnerating a ROM with 6*1 works but 4*1 does not

  VLSIDA/OpenRAM#307 · Filter by author philiprbrenan opened on Sep 4, 2026
  3

• Incorrect internal_power values in generated SKY130 Liberty files

  VLSIDA/OpenRAM#294 · Filter by author Blueonics opened on Apr 30, 2026
  3

• LVS mismatch errors with Sky130 PDK

  VLSIDA/OpenRAM#292 · Filter by author gumnaam2 opened on Apr 19, 2026
  11

• sky130 PEX fails due to missing storage node labels in bitcell_2port

  VLSIDA/OpenRAM#281 · Filter by author DashCodeHub opened on Feb 2, 2026
  3

• FreePDK45 Control Logic Timing - Glitches or Expected Behavior?

  VLSIDA/OpenRAM#276 · Filter by author buchtawill opened on Oct 18, 2025
  2

• Sense amp enable timing error when generating 1 Kb (1024 bits) SRAM — requires manual delay chain adjustment

  VLSIDA/OpenRAM#274 · Filter by author cyberxcodes opened on Oct 16, 2025
  2

• ImportError: Missing 'lef_rom_interconnect' in stable version's OpenRAM tech module

  VLSIDA/OpenRAM#273 · Filter by author OsFlora opened on Aug 18, 2025
  5

  

• Generating SRAM fails at supply_router: Couldn't route from (vdd layer=m3 ...) to to (vdd layer=m3 ...)

  VLSIDA/OpenRAM#268 · Filter by author kammoh opened on May 14, 2025
  3

• Documentation clarifications in basic_usage and basic_setup

  VLSIDA/OpenRAM#262 · Filter by author sampollard opened on Feb 26, 2025
  2

• Assertion Error in SRAM Generation with Specific word_size and num_words Configurations

  VLSIDA/OpenRAM#251 · Filter by author riagus99 opened on Aug 18, 2024
  13

• Error in using sram macro(tiny) in openlane2

  VLSIDA/OpenRAM#247 · Filter by author FriedrichWu opened on Jul 19, 2024
  4

• Runtime

  VLSIDA/OpenRAM#245 · Filter by author mbautista-lab opened on Jun 25, 2024
  13

• ROM >= 8k fails to build

  VLSIDA/OpenRAM#232 · Filter by author urish opened on Mar 28, 2024
  4

• Error in SRAM creation with banks

  VLSIDA/OpenRAM#228 · Filter by author KanishR1 opened on Feb 20, 2024
  10

• LVS mismatch for some sky130 example SRAMs

  VLSIDA/OpenRAM#220 · Filter by author ubfx opened on Dec 27, 2023
  5

• Support for IHP PDK

  enhancementhelp wanted
  VLSIDA/OpenRAM#208 · Filter by author htm23x opened on Oct 26, 2023
  4

• data not getting written into memory cells

  VLSIDA/OpenRAM#199 · Filter by author KolliparaAbhishekAnand opened on Jul 15, 2023
  8

  

• Create yosys memlib mapping

  VLSIDA/OpenRAM#163 · Filter by author xobs opened on Nov 25, 2022
  4