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Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
Verilog 301 48
Power side-channel traces from the Atmega microcontroller and the codes for cross-device deep learning side-channel attack (X-DeepSCA)
Python 10 1
A dataset containing 30 Xbee S2C transmitter data for both including and excluding wireless channel
4
Verilog 2
Test inputs to CS-Audio and recovered audio files
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