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StudentWerk 01 Python Automation for RISC_V Inst set
Python 1 1
Xilinx Open NIC driver to support XXV 10G/25G IP with Open NIC design
Verilog System Design Lab 2023, TUM
C++
Forked from Xilinx/open-nic-shell
AMD OpenNIC Shell includes the HDL source files
SystemVerilog
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