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1. FPGA-Secure-Communication-System FPGA-Secure-Communication-System Public

   Developed a secure communication system using VHDL and Vivado on BASYS3 boards. - Implemented AES encryption on the first board to secure input data, and transmitted the encrypted data via UART. - …

   VHDL 1 1

2. Pong-VHDL-Basys3-VGA Pong-VHDL-Basys3-VGA Public

   Two-player Pong game implemented in VHDL on the Digilent Basys3 (Artix-7) FPGA with VGA 640×480 output

   VHDL 1

3. mini_mips_34 mini_mips_34 Public

   VHDL implementation for a simple five stage pipelined processor, Mini-MIPS, which is a subset of the 32-bit MIPS architecture . Mini-MIPS uses the same 3 instruction formats of MIPS (R, I and J-typ…

   VHDL 1 1

4. Sobel_edge_detection_verilog Sobel_edge_detection_verilog Public

   This project implements the Sobel edge detection algorithm in Verilog for image processing tasks. The Sobel operator is commonly used to detect edges in images by calculating the gradient magnitude…

   Verilog 1

5. ecdsa-bls12381-zynq-accelerator ecdsa-bls12381-zynq-accelerator Public

   Hardware-accelerated ECDSA signature verifier on BLS12-381 — HW/SW co-design on Xilinx Zynq-7000 (RTL in Verilog, ARM C driver, Python test vector suite)

   Verilog