GitHub - MasterPlayer/axis_uart_bridge: FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol · GitHub
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axis_uart_bridge

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

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FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

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fpga zynq xilinx uart systemverilog artix uart-tx axi-stream uart-rx

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