The initial implementation of the N1 processer is complete. The RTL is still unverified. Here are the first synthesys results with Yosys using the iCE40 library:

The “default” configuration of the N1 processor maps all logic to regular PLBs (programmable logic blocks), whereas in the “iCE40UP5K” configuration all adders and multipliers are mapped to four “SB_MAC16” DSP cells.

The cell usage of the N1 compares quite well to the J1, but the N1 seems to require a lot more signal routing.

The first version of the N1 manual has been released. It contains a user spec and an integration guide. An architectural description will be added as the implementation progresses.

The N1 is a little processor, designed with open source EDA tools only. Besides trying out different design and verification flows, my goal is to put this soft IP onto a Lattice ICE40 FPGSA to power my future handheld devices.