CWE - CWE-1224: Improper Restriction of Write-Once Bit Fields (4.20)
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    CWE-1224: Improper Restriction of Write-Once Bit Fields

    Weakness ID: 1224
    Vulnerability Mapping: ALLOWED This CWE ID may be used to map to real-world vulnerabilities
    Abstraction: Base Base - a weakness that is still mostly independent of a resource or technology, but with sufficient details to provide specific methods for detection and prevention. Base level weaknesses typically describe issues in terms of 2 or 3 of the following dimensions: behavior, property, technology, language, and resource.
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    + Description
    The hardware design control register "sticky bits" or write-once bit fields are improperly implemented, such that they can be reprogrammed by software.
    + Extended Description

    Integrated circuits and hardware IP software programmable controls and settings are commonly stored in register circuits. These register contents have to be initialized at hardware reset to define default values that are hard coded in the hardware description language (HDL) code of the hardware unit. A common security protection method used to protect register settings from modification by software is to make the settings write-once or "sticky." This allows writing to such registers only once, whereupon they become read-only. This is useful to allow initial boot software to configure systems settings to secure values while blocking runtime software from modifying such hardware settings.

    Failure to implement write-once restrictions in hardware design can expose such registers to being re-programmed by software and written multiple times. For example, write-once fields could be implemented to only be write-protected if they have been set to value "1", wherein they would work as "write-1-once" and not "write-once".

    + Common Consequences
    Section HelpThis table specifies different individual consequences associated with the weakness. The Scope identifies the application security area that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in exploiting this weakness. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a weakness will be exploited to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.
    Impact Details

    Varies by Context

    		Scope: Confidentiality, Integrity, Availability, Access Control

    System configuration cannot be programmed in a secure way.
    + Potential Mitigations
    Phase(s) Mitigation

    Architecture and Design
    During hardware design, all register write-once or sticky fields must be evaluated for proper configuration.
    + Relationships
    Section Help This table shows the weaknesses and high level categories that are related to this weakness. These relationships are defined as ChildOf, ParentOf, MemberOf and give insight to similar items that may exist at higher and lower levels of abstraction. In addition, relationships such as PeerOf and CanAlsoBe are defined to show similar weaknesses that the user may want to explore.
    + Relevant to the view "Research Concepts" (View-1000)
    Nature Type ID Name
    ChildOf Pillar Pillar - a weakness that is the most abstract type of weakness and represents a theme for all class/base/variant weaknesses related to it. A Pillar is different from a Category as a Pillar is still technically a type of weakness that describes a mistake, while a Category represents a common characteristic used to group related things. 284 Improper Access Control
    + Relevant to the view "Hardware Design" (View-1194)
    Nature Type ID Name
    MemberOf Category Category - a CWE entry that contains a set of other entries that share a common characteristic. 1199 General Circuit and Logic Design Concerns
    + Modes Of Introduction
    Section HelpThe different Modes of Introduction provide information about how and when this weakness may be introduced. The Phase identifies a point in the life cycle at which introduction may occur, while the Note provides a typical scenario related to introduction during the given phase.
    Phase Note
    Architecture and Design
    Implementation Such issues could be introduced during implementation of hardware design, since IP parameters and defaults are defined in HDL code and identified later during Testing or System Configuration phases.
    + Applicable Platforms
    Section HelpThis listing shows possible areas for which the given weakness could appear. These may be for specific named Languages, Operating Systems, Architectures, Paradigms, Technologies, or a class of such platforms. The platform is listed along with how frequently the given weakness appears for that instance.
    Languages

    Verilog (Undetermined Prevalence)

    VHDL (Undetermined Prevalence)

    Technologies

    Class: System on Chip (Undetermined Prevalence)

    + Demonstrative Examples

    Example 1


    Consider the example design module system verilog code shown below. register_write_once_example module is an example of register that has a write-once field defined. Bit 0 field captures the write_once_status value. This implementation can be for a register that is defined by specification to be a write-once register, since the write_once_status field gets written by input data bit 0 on first write.

    (bad code)
    Example Language: Verilog 
    module register_write_once_example
    (
    input [15:0] Data_in,
    input Clk,
    input ip_resetn,
    input global_resetn,
    input write,
    output reg [15:0] Data_out
    );

    reg Write_once_status;

    always @(posedge Clk or negedge ip_resetn)
    if (~ip_resetn)
    begin
    Data_out <= 16'h0000;
    Write_once_status <= 1'b0;
    end
    else if (write & ~Write_once_status)
    begin
    Data_out <= Data_in & 16'hFFFE;
    Write_once_status <= Data_in[0]; // Input bit 0 sets Write_once_status
    end
    else if (~write)
    begin
    Data_out[15:1] <= Data_out[15:1];
    Data_out[0] <= Write_once_status;
    end
    endmodule

    The above example only locks further writes if write_once_status bit is written to one. So it acts as write_1-Once instead of the write-once attribute.

    (good code)
    Example Language: Verilog 
    module register_write_once_example
    (
    input [15:0] Data_in,
    input Clk,
    input ip_resetn,
    input global_resetn,
    input write,
    output reg [15:0] Data_out
    );

    reg Write_once_status;

    always @(posedge Clk or negedge ip_resetn)
    if (~ip_resetn)
    begin
    Data_out <= 16'h0000;
    Write_once_status <= 1'b0;
    end
    else if (write & ~Write_once_status)
    begin
    Data_out <= Data_in & 16'hFFFE;
    Write_once_status <= 1'b1; // Write once status set on first write, independent of input
    end
    else if (~write)
    begin
    Data_out[15:1] <= Data_out[15:1];
    Data_out[0] <= Write_once_status;
    end

    endmodule


    + Weakness Ordinalities
    Ordinality Description
    Primary
    (where the weakness exists independent of other weaknesses)
    + Detection Methods
    Method Details

    Automated Analysis
    Use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.
    + Memberships
    Section HelpThis MemberOf Relationships table shows additional CWE Categories and Views that reference this weakness as a member. This information is often useful in understanding where a weakness fits within the context of external information sources.
    Nature Type ID Name
    MemberOf CategoryCategory - a CWE entry that contains a set of other entries that share a common characteristic. 1396 Comprehensive Categorization: Access Control
    + Vulnerability Mapping Notes
    Usage ALLOWED
    (this CWE ID may be used to map to real-world vulnerabilities)
    Reason Acceptable-Use

    Rationale

    		This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.

    Comments

    		Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
    + Content History
    + Submissions
    Submission Date Submitter Organization
    2019-12-12
    (CWE 4.0, 2020-02-24)     		Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi Intel Corporation
    + Modifications
    Modification Date Modifier Organization
    2025-12-11
    (CWE 4.19, 2025-12-11)     		CWE Content Team MITRE
    updated Detection_Factors, Potential_Mitigations, Weakness_Ordinalities
    2023-06-29
    (CWE 4.12, 2023-06-29)     		CWE Content Team MITRE
    updated Mapping_Notes
    2023-04-27
    (CWE 4.11, 2023-04-27)     		CWE Content Team MITRE
    updated Relationships
    2022-10-13
    (CWE 4.9, 2022-10-13)     		CWE Content Team MITRE
    updated Demonstrative_Examples
    2022-04-28
    (CWE 4.7, 2022-04-28)     		CWE Content Team MITRE
    updated Related_Attack_Patterns
    2020-08-20
    (CWE 4.2, 2020-08-20)     		CWE Content Team MITRE
    updated Related_Attack_Patterns
    Page Last Updated: April 30, 2026